The RISC-V Reader: An Open Architecture Atlas
Product ID: 81766718
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The RISC-V Reader is a concise introduction and reference for embedded systems programmers, students, and the curious to a modern, popular, open architecture. RISC-V spans from the cheapest 32-bit embedded microcontroller to the fastest 64-bit cloud computer. The text shows how RISC-V followed the good ideas of past architectures while avoiding their mistake. Highlights include: Introduces the RISC-V instruction set in only 100 pages, including 75 figures An Instruction Translator Guide to help translate assembly language programs from ARM-32 and x86-32 instruction sets to RISC-V 2-page RISC-V Reference Card that summarizes all instructions 50-page Instruction Glossary that defines every instruction in detail 75 spotlights of good architecture design using margin icons 50 sidebars with interesting commentary and RISC-V history 25 quotes to pass along wisdom of noted scientists and engineers Ten chapters introduce each component of the modular RISC-V instruction set--often contrasting code compiled from C to RISC-V versus the older ARM, Intel, and MIPS architectures--but readers can start programming after Chapter 2. Praise for The RISC-V Reader: “This timely book concisely describes the simple, free and open RISC-V ISA that is experiencing rapid uptake in many different computing sectors.” Krste Asanovic, University of California, Berkeley, one of the four architects of RISC-V “I like RISC-V and this book as they are elegant—brief, to the point, and complete.” C. Gordon Bell, a computer architecture pioneer “ This handy little book effortlessly summarizes all the essential elements of the RISC-V Instruction Set Architecture, a perfect reference guide for students and practitioners alike.” Professor Randy Katz, University of California, Berkeley, one of the inventors of RAID storage systems “This clearly-written book offers a good introduction to RISC-V, augmented with insightful comments on its evolutionary history and comparisons with other familiar architectures.” John Mashey, one of the designers of the MIPS architecture “This book tells what RISC-V can do and why its designers chose to endow it with those abilities.” Ivan Sutherland, the father of computer graphics “RISC-V will change the world, and this book will help you become part of that change.” Professor Michael B. Taylor, University of Washington “This book will be an invaluable reference for anyone working with the RISC-V ISA.” Megan Wachs, PhD, SiFive Engineer Review: Great reference! - This offers an exceptional introduction to the RISC instruction set. I've seen other reduced instruction set computers - RISCs in the generic sense or gRISCs for now - but I find this distinctive in several ways. Regularity and orthogonality are nearly defining features of gRISCs, and RISC-V shares that. It goes farther, though. RISC-V, like gRISCs ARM and MIPS, has a compressed instruction format. But, unlike the others, RISC-V compressed instructions form a proper subset of the full-length instructions - regularity of yet another kind. Also like others, different RISC-V implementations might omit or include parts of the instruction set. Unlike the others, though, RISC-V clearly defines subsets, like floating point or vector operations, making it a bit easier for programmers to remember what's supported in any specific implementation. The modular instruction set also makes it easy for chip builders to trade off features and performance against complexity and cost in predictable ways. As an aside, part of Patterson's reason for gRISC architecture in the first place was a belief that complex instruction sets were more likely to have instruction set bugs. A few high-profile cases, the Pentium FDIV bug being just one, certainly corroborate that belief. The more recent Spectre and Meltdown vulnerabilities, though not directly related to CISC vs. gRISC issues, also point out how increasing processor complexity increases the chance of implementation problems. I recommend this, not just to RISC-V programmers, but to anyone with an interest in modern processors. Although the RISC-V architecture is designed to be independent of any particular implementation, processor implementors will also find it very useful. -- wiredweird Review: One of the developers is an author - Nice coverage of the RISC-V instruction set and what led to the development and why it is implemented like it is. Compares it with ARM and Intel processor instructions. Covers assembly language.
| Best Sellers Rank | #144,008 in Books ( See Top 100 in Books ) #207 in Computer Hardware & DIY |
| Customer Reviews | 4.6 out of 5 stars 164 Reviews |
W**D
Great reference!
This offers an exceptional introduction to the RISC instruction set. I've seen other reduced instruction set computers - RISCs in the generic sense or gRISCs for now - but I find this distinctive in several ways. Regularity and orthogonality are nearly defining features of gRISCs, and RISC-V shares that. It goes farther, though. RISC-V, like gRISCs ARM and MIPS, has a compressed instruction format. But, unlike the others, RISC-V compressed instructions form a proper subset of the full-length instructions - regularity of yet another kind. Also like others, different RISC-V implementations might omit or include parts of the instruction set. Unlike the others, though, RISC-V clearly defines subsets, like floating point or vector operations, making it a bit easier for programmers to remember what's supported in any specific implementation. The modular instruction set also makes it easy for chip builders to trade off features and performance against complexity and cost in predictable ways. As an aside, part of Patterson's reason for gRISC architecture in the first place was a belief that complex instruction sets were more likely to have instruction set bugs. A few high-profile cases, the Pentium FDIV bug being just one, certainly corroborate that belief. The more recent Spectre and Meltdown vulnerabilities, though not directly related to CISC vs. gRISC issues, also point out how increasing processor complexity increases the chance of implementation problems. I recommend this, not just to RISC-V programmers, but to anyone with an interest in modern processors. Although the RISC-V architecture is designed to be independent of any particular implementation, processor implementors will also find it very useful. -- wiredweird
L**N
One of the developers is an author
Nice coverage of the RISC-V instruction set and what led to the development and why it is implemented like it is. Compares it with ARM and Intel processor instructions. Covers assembly language.
A**B
Very informative. A bit technical.
This book is great for anyone looking to get into RISC-V development. I do suggest a background in programming as it can be a bit technical.
F**O
The author is Definitely a cheerleader for RISC-V but excellent for learning HOW RISC WORKS
Author is very pro RISC v, but this is documented by examples. An excellent way to learn how RISC-V works - as long as you don't work for an ARM based company
M**.
Good reference
Well written provides details not found in RISC-V specs good addition to RISC-V understanding not simply a printed version of what's already available like other books published on trending tech. All instructions identified with clear descriptions but unfortunately alphabetical so all options are intermixed.
M**A
Concise, clear and beautifully written
Short, concise, and to the point. You will walk away with two outcomes. The first, an appreciation for the elegance and simplicity of a modern CPU processor. The second, a deep desire to change to join a revolution to get this processor adopted everywhere.
J**N
Excelente
10/10. Explica cada detalle sobre RISC-V
E**X
Covers architecture and assembler instructions.
Book has good clear examples of Risc-V instructions. It is well written and complete.
Y**N
The RISC-V Reader
The book is very useful to learn risc-v
N**Y
Essential reading and reference for the new-to-Risc-V world.
This book introduces and covers the RISC-V instruction set architecture in a comprehensive way. Regular comparisons are made with several ARM and x86 processor types. Many very useful program coding examples are provided. Plenty of architecture discussions such as how the RISC-V delivers shorter code sequences than ARM or x86 yet has less hardware to implement into CPU logic. Many advanced features explained. A comprehensive and useful 45 page listing of the instructions is provided. In total 180 pages of excellent RISC-V technical details.
M**J
Easy to read intro to the RV ISA and the decisions & trade-offs behind it
Easy to read, inspiring introduction to the RV ISA. With many interesting anecdotes and comparisons to other major ISAs
M**N
Une introduction et une référence à la fois
Excellente introduction au jeu d'instruction RISC-V d'un côté et livre de référence de l'autre. On commence par le lire d'un bout à l'autre puis on continue à s'en servir comme référence. Le livre, dans sa préface, propose de soumettre les errata sur son site web où la liste des errata sera disponible aussi. Malheureusement ce n'est pas ou plus le cas. Il y a 2-3 petits typos que j'aurais voulu soumettre. Aussi j’apprécierais une nouvelle édition avec la version finale de l'extension RV ainsi que d'autres nouveauté introduites depuis 2017. Si une seconde édition voit le jour, je la commande immédiatement. D'ici là ça reste mon livre de référence. Lorsque ce livre ne suffit pas, c'est directement dans les spécifications ISA qu'il faut regarder. A recommander absolument.
J**E
risc-v assembler
EL libro está bien pero está escrito como deprisa y corriendo y algunas cosas que son sencillas las convierten en complicadas. Necesitaría una segunda versión mejorada.
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